Compositions for planarizing or polishing the surface of a substrate are well known in the art. Polishing slurries typically contain an abrasive material in an aqueous solution and are applied to a surface by contacting the surface with a polishing pad saturated with the slurry composition. Typical abrasive materials include silicon dioxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. U.S. Pat. No. 5,527,423, for example, describes a method for chemically-mechanically polishing a metal layer by contacting the surface with a polishing slurry comprising high purity fine metal oxide particles in an aqueous medium.
Conventional polishing compositions typically are not entirely satisfactory at planarizing semiconductor wafers or integrated circuits having alternating layers of conductive metal and insulating material, e.g., silicon dioxide, that require planar surfaces. In particular, polishing slurries can have less than desirable polishing rates, and their use in chemically-mechanically polishing semiconductor surfaces can result in poor surface quality. Because the performance of a semiconductor wafer is directly associated with the planarity of its surface, it is crucial to use a polishing composition that has a high polishing efficiency, uniformity, and removal rate and leaves a high quality polish with minimal surface defects.
The difficulty in creating an effective polishing composition for semiconductor wafers stems from the complexity of the semiconductor wafer. Semiconductor wafers are typically composed of a substrate, on which a plurality of transistors are formed. Integrated circuits are physically connected into the substrate by patterning metal and insulating layers while interconnecting desired metal regions through intermediate insulating, e.g., SiO2, layers. To produce an operable semiconductor wafer and to maximize the yield, performance, and reliability of the wafer, it is desirable to polish selected surfaces of the wafer without adversely affecting underlying structures or topography. Various problems in semiconductor fabrication can occur if the process steps are not performed on wafer surfaces that are adequately planarized.
There have been many attempts to improve the polishing efficiency and uniformity of conventional polishing agents, while minimizing defects in the polished surface and damage to underlying structures or topography. For example, U.S. Pat. No. 5,340,370 describes a polishing composition comprising an abrasive, an oxidizing agent, and water, which purportedly yields an improved removal rate and polishing efficiency. Similarly, U.S. Pat. No. 5,622,525 describes a polishing composition comprising colloidal silica having an average particle size of 20-50 nm, a chemical activator, and demineralized water.
A need remains, however, for compositions and methods that will exhibit desirable planarization efficiency, uniformity, and removal rate during the polishing and planarization of substrates, particularly semiconductor wafer surfaces, while minimizing defects, such as surface imperfections and damage to underlying structures and topography during polishing and planarization.